/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 12.1 EDK_MS1.53d
* DO NOT EDIT.
*
* Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

* 
* Description: Driver parameters
*
*******************************************************************/

#define STDIN_BASEADDRESS 0x84000000
#define STDOUT_BASEADDRESS 0x84000000

/******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral RS232_UART */
#define XPAR_RS232_UART_BASEADDR 0x84000000
#define XPAR_RS232_UART_HIGHADDR 0x8400FFFF
#define XPAR_RS232_UART_DEVICE_ID 0
#define XPAR_RS232_UART_BAUDRATE 115200
#define XPAR_RS232_UART_USE_PARITY 0
#define XPAR_RS232_UART_ODD_PARITY 0
#define XPAR_RS232_UART_DATA_BITS 8


/******************************************************************/


/* Canonical definitions for peripheral RS232_UART */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_UARTLITE_0_HIGHADDR 0x8400FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN -1


/******************************************************************/

/* Definitions for driver MULTIPLY */
#define XPAR_MULTIPLY_NUM_INSTANCES 1

/* Definitions for peripheral MULTIPLY_0 */
#define XPAR_MULTIPLY_0_DEVICE_ID 0
#define XPAR_MULTIPLY_0_BASEADDR 0xC0A00000
#define XPAR_MULTIPLY_0_HIGHADDR 0xC0A0FFFF


/******************************************************************/


/* Definitions for peripheral XPS_BRAM_IF_CNTLR_0 */
#define XPAR_XPS_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
#define XPAR_XPS_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF


/******************************************************************/

/* Definitions for bus frequencies */
#define XPAR_CPU_PPC405_DPLB0_FREQ_HZ 100000000
#define XPAR_CPU_PPC405_IPLB0_FREQ_HZ 100000000
/******************************************************************/

/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
/******************************************************************/

#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 100000000

/******************************************************************/

#define XPAR_CPU_ID 0
#define XPAR_PPC405_VIRTEX4_ID 0
#define XPAR_PPC405_VIRTEX4_DPLB0_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB0_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_FASTEST_PLB_CLOCK DPLB0
#define XPAR_PPC405_VIRTEX4_GENERATE_PLB_TIMESPECS 1
#define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100
#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x000001FF
#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1
#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0
#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1
#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
#define XPAR_PPC405_VIRTEX4_HW_VER "2.01.b"

/******************************************************************/